← 返回 JSSC 论文列表JSSC 2007第3期Data Converters0.18μmDelta-Sigma ADCDAC
A 0.5-V 74-dB SNDR 25-kHz Continuous-Time Delta-Sigma Modulator With a Return-to-Open DAC
0.5V低功耗连续时间ΔΣ调制器，采用返回开路架构实现74dB SNDR。
0.5V, 74dB SNDR, 25kHz带宽, 300μW功耗
连续时间ΔΣ调制器超低压设计返回开路架构体输入技术低功耗
▸返回开路架构实现超低压RZ反馈DAC
▸体输入门控时钟比较器
▸体输入跨导放大器用于有源RC环路滤波器
Abstract
A 0.5-V third-order one-bit fully-differential contin- uous-time /1/6 modulator is presented. The presented modulator architecture uses true low-voltage design techniques, and does not require internal voltage boosting or low-threshold devices. A return-to-open architecture that enables the ultra-low-voltage realization of return-to-zero signaling for the feedback DAC is proposed. The ultra-low-voltage operation is further enabled by a body-input gate-clocked comparator, and body-input operational transconductance amplifiers for the active- RC loop filter. Fabri- cated on a 0.18- m CMOS process, the modulator achieves a peak SNDR of 74 dB in a 25 kHz bandwidth, and occupies an area of 0.6 mm /50; the modulator core consumes 300 W.