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A 10-bit 50-MS/s Pipelined ADC With Opamp
该论文介绍了一种采用运放电流复用技术的10位50-MS/s流水线ADC，实现了低功耗和高性能。
1.8V, 50MS/s, 18mW, 9.2/8.8 ENOB
流水线ADC电流复用低功耗电容电平位移NMOS输入级
▸创新点1：运放偏置电流复用技术（方法创新） - 通过双输入偏置电流复用运放设计，实现单个运放完成两个运放的功能，显著降低功耗至220μW/MHz，同时支持每时钟周期重置运放求和节点，提升系统效率。
▸创新点2：电容电平位移技术（电路创新） - 采用电容电平位移器简化增益提升放大器设计，仅需NMOS输入级即可实现快速运放稳定，降低功耗的同时保持高精度（ENOB 9.2/8.8）。
▸创新点3：仅NMOS输入级的简化设计（电路创新） - 摒弃传统互补输入级，通过纯NMOS输入结构优化噪声和功耗，支持1.62-1.96V宽电压范围和0-85℃温度稳定性，实测ENOB损失极小。
▸创新点4：低功耗高鲁棒性系统集成（系统创新） - 整合电流复用与电平位移技术，在50MS/s采样率下实现18mW总功耗（模拟部分11mW），芯片面积仅0.49mm²（0.18μm CMOS工艺），兼具高能效与小尺寸。
Abstract
Power and area saving concepts such as opera- tional amplifier (opamp) bias current reuse and capacitive level shifting are used to lower the analog power of a 10-bit pipelined analog-to-digital converter (ADC) to 220 W/MHz. Since a dual-input bias current reusing opamp performs as two opamps, the opamp summing nodes can be reset in every clock cycle. By using only N-channel MOS (NMOS) input stages, the capacitive level shifter simplifies the gain-boosting amplifier design and enables fast opamp settling with low power-consumption. The prototype achieves 9.2/8.8 effective number of bits (ENOB) for 1- and 20-MHz inputs at 50 MS/s. The ADC works within the temperature range of 0 to 85 C and the supply voltage from 1.62 to 1.96 V with little measured loss in the ENOB. The chip consumes 18 mW (11 mW for the analog portion of the ADC and 7 mW for the rest including buffers) at 1.8 V , and the active area occupies /49 /49 /49 /51mm/50using a 0.18- m complementary metal oxide semiconductor (CMOS) process.