A 13-b Linear, 40-MS/s Pipelined ADC With Self-Configured

Abstract

Using statistical matching properties of capac- itor arrays, a pipelined ADC self-configures the multiplying digital-to-analog converter (MDAC) capacitor array for best matching from many trial combinations of smaller capacitive sub-elements. These sub-elements having opposite error mag- nitudes are grouped together to form matched elements thus permitting an accurate multi-bit MDAC to be created without using an explicit trimming network. A random search algorithm enables the self-configuration process by quickly regrouping the sub-elements to reduce the spread between the reconstructed elements. The proposed state machine based permutation algo- rithm allows near unique permutations of the sub-elements and achieves a near unity state repetition ratio with a simple hardware implementation. An analog-to-digital converter (ADC) system is designed with the self-configuration algorithm contained in the same die, and improvement in capacitor matching is demonstrated after the self-configuration process. A 0.18- m CMOS prototype achieves 13-b linearity and over 80-dB spurious-free dynamic range (SFDR) at 43 MS/s. The chip consumes 268 mW at 1.8 V and occupies 3.6 mm /50.