A 256-kb 65-nm Sub-threshold SRAM Design for Ultra-Low-V oltage Operation

Abstract

Low-voltage operation for memories is attractive because of lower leakage power and active energy, but the chal- lenges of SRAM design tend to increase at lower voltage. This paper explores the limits of low-voltage operation for traditional six–transistor (6 T) SRAM and proposes an alternative bitcell that functions to much lower voltages. Measurements confirm that a 256-kb 65-nm SRAM test chip using the proposed bitcell operates into sub-threshold to below 400 mV. At this low voltage, the memory offers substantial power and energy savings at the cost of speed, making it well-suited to energy-constrained applications. The paper provides measured data and analysis on the limiting effects for voltage scaling for the test chip.