← 返回 JSSC 论文列表JSSC 2007第3期Clocking & PLLs0.13-μm InP HEMT
A 50-Gbit/s 450-mW Full-Rate 4:1 Multiplexer With Multiphase Clock Architecture in 0.13-/22m InP HEMT Technology
一款用于40 Gbit/s以上光通信系统的全速率4:1复用器，采用多相位时钟架构。
0.13-μm InP HEMT, 1.5V, 50-Gbit/s, 450mW, 283fs rms抖动
全速率复用器多相位时钟光通信系统D型触发器低功耗
▸创新点1：基于D型触发器（DFF）的重定时器设计，通过优化时序控制实现75-Gbit/s的高速操作，显著提升数据传输速率和稳定性。该方法创新通过精确的时钟同步减少了时序偏差，适用于高速光通信系统。
▸创新点2：采用EXOR型延迟缓冲器的时钟树系统，有效匹配数据路径的时序偏差，确保50-Gbit/s数据传输的准确性。这一电路创新通过动态调整时钟相位，降低了信号抖动（283 fs rms），提升了系统整体性能。
▸创新点3：多相位时钟生成器设计，支持超过四通道的串行化处理，扩展了系统的多路复用能力。该系统创新通过多相位时钟分配，实现了高吞吐量和低功耗（450 mW @ 1.5 V）的平衡。
▸创新点4：通过电压分配分析将供电电压降至1.5 V，在保持50-Gbit/s高速操作的同时优化了功耗效率。这一电路创新在0.13-μm InP HEMT工艺下实现了高性能与低功耗的协同设计。
Abstract
A full-rate multiplexer (MUX) with a multiphase clock architecture for over 40 Gbit/s optical communication systems is presented. The 4:1 MUX is comprised of a re-timer based on a D-type flip-flop (DFF) and a clock tree system that uses EXOR-type delay buffers to match its skews well to those of the data. The supply voltage is reduced to 1.5 V by ana- lyzing the voltage allocation. Fabricated in a 0.13- m InP HEMT technology, a DFF test circuit achieved 75-Gbit/s operation and exhibited performance sufficient to re-time 50-Gbit/s serialized data. The 4:1 MUX measurement results demonstrate successful 50-Gbit/s operation at room temperature, and 40-Gbit/s operation, which has /49/48 /49/49error free for /50/51/49 /49pseudorandom bit stream (PRBS) data, up to an ambient temperature of 90 degrees or down to 1.24 V of supply voltage. The circuit consumes 450 mW at a 1.5-V supply and exhibits an output jitter of 283 fs rms at 50-Gbit/s operation. We also propose a multiphase clock generator for a MUX that has a serialization of more than four channels.