JSSC 2007第3期Clocking & PLLs0.18μmNeural Network Accelerator

A Fully Differential Low-Power Divide-by-8 Injection-Locked Frequency Divider Up to 18 GHz

一种低功耗全差分8分频注入锁定频率分频器，具有高工作频率和低功耗特性。

TSMC 0.18μm CMOS, 1.8V, 3.6mW, 4-18GHz

频率分频器注入锁定低功耗全差分CML逻辑

▸创新点1：采用四级CML D锁存器环形结构，通过级联四个电流模式逻辑（CML）D锁存器形成环形拓扑，显著提高了工作频率范围（4 GHz至18 GHz），同时降低了功耗（3.6 mW），相比传统静态分频器具有更高的频率适应性和能效比。

▸创新点2：全差分设计扩大锁定范围，通过差分信号注入锁存器的时钟端，实现了锁定范围与中心频率比例高达50%的性能，且中心频率不受注入幅度影响，解决了传统注入锁定分频器依赖注入信号的局限性。

▸创新点3：提出新型注入锁定机制，通过将输入信号注入环形结构的时钟端而非数据端，优化了相位噪声和抖动性能，同时保持宽锁定范围（覆盖毫米波频段），适用于高频低功耗应用场景。

▸创新点4：采用TSMC 0.18μm CMOS工艺实现，通过优化偏置条件和晶体管尺寸，在1.8V电源电压下达成18 GHz高频操作，验证了该结构在先进工艺节点下的可扩展性和鲁棒性。

Abstract

A low power divide-by-8 injection-locked frequency divider is presented. The frequency divider consists of four cur- rent-mode logic (CML) D-latches connected in the form of a four-stage ring with the differential input signal injected into the clock terminals of the latches. The output signals can be taken from the data terminals of any of the four latches. The proposed frequency divider has higher operating frequency and lower power dissipation compared with conventional static frequency dividers. Compared with existing injection-locked frequency dividers, the proposed fully differential frequency divider presents wider locking range with the center frequency independent of in- jection amplitude. The frequency divider is implemented in TSMC 0.18 m CMOS technology. It consumes around 3.6 mW power with 1.8 V supply. The operating frequency can be tuned from 4 GHz to 18 GHz. The ratio of the locking range over the center frequency is up to 50% depending on the operating frequency and biasing conditions.