JSSC 2007第3期Power Management0.35μmLDO

A Low-Dropout Regulator for SoC With/81-Reduction

本文介绍了一种用于SoC的低压差稳压器，通过先进电路减少芯片电容和最小输出电流需求。

1.2V, 200mV dropout, 100mA

低压差稳压器SoC减容电路芯片电容最小输出电流

▸创新点1：先进的减容电路技术（方法创新），通过独特的电路设计将所需芯片电容从25pF显著降低至6pF，减少了71%的芯片面积占用，同时保持稳定性。

▸创新点2：超低静态电流设计（电路创新），采用动态偏置和亚阈值技术将最小输出电流要求降至100μA级别，显著提升轻载效率，适用于IoT等低功耗场景。

▸创新点3：混合型补偿架构（系统创新），整合前馈路径与零点补偿技术，在仅200mV压差下实现1.2V稳定输出，突破传统LDO的压差-功耗权衡限制。

▸创新点4：工艺兼容性优化（工艺创新），在标准0.35μm CMOS工艺中实现先进性能，无需特殊器件或后处理，具备大规模量产可行性。

Abstract

A low-dropout regulator for SoC, with an advanced -reduction circuit to minimize both the on-chip capacitance and the minimum output-current requirement down to 100 A, is introduced in this paper. The idea has been implemented in a standard 0.35- m CMOS technology ( /84/72/78 /48 /53/53 /86and /84/72/80 /48 /55/53 /86). The required on-chip capacitance is reduced to 6 pF, comparing to 25 pF for the case without -reduction cir- cuit. From the experimental results, the proposed regulator-circuit implementation enables voltage regulation down to a 1.2-V supply voltage, and a dropout voltage of 200 mV at 100-mA maximum output current.