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A Low-Spurious Low-Power 12-bit 160-MS/s DAC in 90-nm CMOS for Baseband
提出了一种低杂散低功耗12位160MS/s DAC，适用于基带无线发射器。
74 dB SFDR, 55 dB SNDR, 73 dB THD, 1.3/2.6 V dual supply
DAC低杂散低功耗基带无线封装应力
▸创新点1：引入退化电流开关（方法创新）。通过优化电流开关结构，显著降低DAC的杂散噪声，实现了74 dB的SFDR（无杂散动态范围），提升了信号纯净度。
▸创新点2：分析封装应力下的失配行为（方法创新）。研究了薄芯片封装导致的应力对载流子迁移率的影响，提出了补偿策略，减少了I/Q通道的失配问题。
▸创新点3：采用双电源供电设计（电路创新）。使用1.3V/2.6V双电源供电，在保证12-bit精度的同时将功耗控制在4mA，实现了低功耗与高性能的平衡。
▸创新点4：高集成度数字处理器协同设计（系统创新）。在90nm CMOS工艺中集成DAC核心与数字处理器，优化了信号路径，实现了55 dB SNDR和73 dB THD的高性能指标。
Abstract
A low-spurious low-power 12-bit 160-MS/s digital to analog converter (DAC) for baseband wireless transmitter is pro- posed and demonstrated. Degenerated current switches are intro- duced and benefits of using them are discussed. Mismatch behavior under packaging-induced die stress is also presented. The mobility shift caused by package stress inherited from a thin-die is a domi- nant source of I/Q mismatch. A 2-channel I/Q DAC core consumes 4 mA with a 1.3/2.6 V dual supply. The 0.13 mm /50I/Q DAC core fabricated in 90-nm digital CMOS process with a highly-integrated digital processor achieves 74 dB SFDR, 55 dB SNDR, and 73 dB THD for a 975 kHz sinusoid at 153.6 MS/s sample rate.