← 返回 JSSC 论文列表JSSC 2007第4期Data Converters0.18μmPipeline ADCNeural Network Accelerator
A 1-V 100-MS/s 8-bit CMOS Switched-Opamp Pipelined ADC Using Loading-Free Architecture
1V供电下采用无负载架构的8位100MS/s流水线ADC，性能媲美高压ADC。
0.18μm CMOS, 1V, 100MS/s, SNR 45.2dB, SNDR 41.5dB, SFDR 52.6dB, DNL 0.5LSB, INL 1.1LSB, 30mW
低电压流水线ADC开关运放双采样无负载架构
▸创新点1：无负载架构减少电容负载 - 提出了一种新颖的无负载架构，通过优化电路设计减少电容负载，显著提高了低电压开关运放（SO）电路的速度和效率，使ADC在1-V电源下实现100-MS/s的转换速率。
▸创新点2：双采样技术提高速度 - 采用双采样技术，通过并行采样和处理信号，有效提升了ADC的采样速率和整体性能，使其在低电压条件下仍能保持高转换速率。
▸创新点3：快速唤醒双输入双输出可切换运放 - 设计了一种快速唤醒的双输入双输出可切换运放，显著降低了电路的唤醒时间，提高了动态响应速度，从而支持高速数据转换。
▸创新点4：低功耗高性能设计 - 在0.18微米CMOS工艺下实现，芯片仅消耗30 mW功耗，同时达到峰值SNR 45.2 dB、SNDR 41.5 dB和SFDR 52.6 dB的高性能指标，展示了低电压下的高效能设计。
Abstract
A 1-V , 8-bit pipelined ADC is realized using multi-phase switched-opamp (SO) technique. A novel loading-free architecture is proposed to reduce the capacitive loading and to improve the speed in low-voltage SO circuits. Employing the proposed loading-free pipelined ADC architecture to- gether with double-sampling technique and a fast-wake-up dual-input–dual-output switchable opamp, the ADC achieves 100-MS/s conversion rate, which to our knowledge is the fastest ADC ever reported at 1-V supply using SO technique, with perfor- mance comparable to that of many high-voltage switched-capac- itor (SC) ADCs. Implemented in a 0.18- m CMOS process, the ADC obtains a peak SNR of 45.2 dB, SNDR of 41.5 dB, and SFDR of 52.6 dB. Measured DNL and INL are 0.5 LSB and 1.1 LSB, respectively. The chip dissipates only 30 mW from a 1-V supply.