← 返回 JSSC 论文列表JSSC 2007第4期Data Converters0.35μm CMOSPipeline ADC
A 12-Bit 75-MS/s Pipelined ADC Using
提出一种利用不完全建立技术的低功耗流水线ADC设计
12-bit, 75-MS/s, 65.6 dB SNDR, 273 mW
流水线ADC不完全建立开环放大器低功耗设计混合信号技术
▸创新点1：采用不完全建立技术降低功耗，通过优化放大器设计，显著减少功耗，实现60%的放大器功耗降低，提升能效。
▸创新点2：开环残差放大器设计，与传统闭环设计相比，简化电路结构，降低复杂度，同时保持高性能，适用于高速ADC应用。
▸创新点3：混合信号技术优化，结合模拟与数字信号处理，提升系统整体性能，实现65.6 dB的SNDR，确保高精度转换。
▸创新点4：在0.35微米CMOS工艺下实现，芯片面积仅为7.9 mm²，功耗273 mW，展示高效集成与低功耗设计能力。
Abstract
The residue amplifiers in high-speed pipelined analog-to-digital converters (ADCs) typically determine the con- verter’s overall speed and power performance. We propose a mixed-signal technique that exploits incomplete settling to achieve low power residue amplification. In the first stage of a 12-bit, 75-MS/s proof-of-concept prototype, the employed open-loop residue amplifier dissipates only 2.9 mW from a 3-V supply, achieving 60% amplifier power reduction over a previously re- ported open-loop residue amplifier implementation and achieving 90% amplifier power reduction over a conventional opamp implementation. Test results show that the converter’s maximum signal-to-noise-and-distortion ratio (SNDR) is 65.6 dB. The mea- sured integral and differential nonlinearity are 0.95 LSB and 0.64 LSB, respectively. The experimental chip occupies 7.9 mm /50and consumes 273 mW in a 0.35- m double-poly, quadruple-metal CMOS process.