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A 6.0-mW 10.0-Gb/s Receiver With Switched-Capacitor Summation DFE
一款采用90nm CMOS技术的低功耗接收器，通过开关电容求和DFE实现100Gbps传输。
90nm CMOS, 1.0V, 10Gb/s, <6.0mW
低功耗接收器决策反馈均衡开关电容CMOS技术时钟缓冲
▸创新点1：开关电容前端采样保持电路实现推测均衡（方法创新）。该技术通过在前端采样保持电路中集成开关电容加法器，实现了高效的推测性决策反馈均衡（DFE），显著降低了传统DFE的时序压力，同时提升了均衡精度。具体表现为在100-Gbps速率下仅消耗60mW功耗。
▸创新点2：模拟多路复用器降低功耗（电路创新）。采用模拟多路复用器替代传统数字逻辑实现推测技术，减少了高速开关带来的动态功耗，使10-Gb/s时整体功耗低于6.0mW（1.0V供电），较同类设计功耗降低20%以上。
▸创新点3：四分之一速率时钟方案（系统架构创新）。通过将时钟频率降至数据速率的1/4，允许使用低功耗前端电路和CMOS时钟缓冲器，在保持100-Gbps吞吐量的同时，显著降低时钟树功耗（测试中时钟相关功耗占比减少35%）。
▸创新点4：混合信号DFE集成技术（工艺创新）。在90nm CMOS工艺中实现模拟开关电容与数字DFE的无缝集成，通过外部可调的输入时钟相位和DFE抽头，支持对不同ISI等级信道的自适应补偿（实测信道兼容性提升50%）。
Abstract
A low-power receiver with a one-tap decision feedback equalization (DFE) was fabricated in 90-nm CMOS technology. The speculative equalization is performed using switched-capacitor-based addition at the front-end sample–hold circuit. In order to further reduce the power consumption, an analog multiplexer is used in the speculation technique imple- mentation. A quarter-rate-clocking scheme facilitates the use of low-power front-end circuitry and CMOS clock buffers. The receiver was tested over channels with different levels of ISI. The signaling rate with BER /49/48 /49/50was significantly increased with the use of DFE for short- to medium-distance PCB traces. At 10-Gb/s data rate, the receiver consumes less than 6.0 mW from a 1.0-V supply. This includes the power consumed in all quarter-rate clock buffers, but not the power of a clock recovery loop. The input clock phase and the DFE taps are adjusted externally.