A 65-nm SoC Embedded 6T-SRAM Designed for Manufacturability With Read and Write Operation

Abstract

In the sub-100-nm CMOS generation, a large local Vth variability degrades the 6T-SRAM cell stability, so that we have to consider this local variability as well as the global vari- ability to achieve high-yield SRAM products. Therefore, we need to employ some assist circuits to expand the SRAM operating margin. We propose a variability-tolerant 6T-SRAM cell layout and new circuit techniques to improve both the read and the write oper- ating margins in the presence of a large Vth variability. By ap- plying these circuit techniques to a 0.494- m/50SRAM cell with a ratio of 1, which is an extremely small cell size, we can achieve a high-yield 8M-SRAM for a wide range of Vth values using a 65-nm low stand-by power (LSTP) CMOS technology.