JSSC 2007第4期Power ManagementCMOS兼容SOI工艺

A Conﬁgurable Enhanced TTRAM Macro for System-Level Power Management Uniﬁed Memory Fukashi Morishita, Isamu Hayashi, Takayuki Gyohten, Hideyuki Noda, Takashi Ipposhi, Hiroki Shimano

采用主动体偏置技术的增强型TTRAM，实现低电压操作和高性能。

263 MHz @ 0.8V, 10.2 mW @ 0.5V

TTRAM低电压操作体偏置控制系统级电源管理高密度存储器

▸创新点1：主动体偏置控制技术（Active Body-Bias Control Technique）通过动态调节晶体管体偏置电压，显著降低工作电压至0.5V，同时保持263MHz高频性能，属于电路级创新。该技术解决了传统TTRAM在低电压下稳定性差的问题，且无需额外负电压源。

▸创新点2：无负电压源设计（Negative Voltage-Free Design）通过优化存储单元结构和偏置策略，完全消除对负电压源的依赖，简化了电源管理系统的复杂度，属于系统级创新。这一设计使得ET2RAM更易于集成到SoC中。

▸创新点3：统一电源管理宏架构（Unified Power Management Macro）将存储与控制逻辑整合为可配置模块，支持动态电压频率调节（DVFS），适用于系统级电源管理，属于架构创新。其10.2mW@0.5V的功耗表现优于传统方案。

▸创新点4：工艺兼容性与高密度（CMOS-SOI Compatibility & High Density）采用标准SOI工艺实现高密度存储阵列，同时通过单元结构优化提升存储效率（higher cell efficiency），属于工艺与电路协同创新。

Abstract

A twin-transistor random access memory (TTRAM) can provide high speed, low power and high density with CMOS compatible SOI process. However it is difﬁcult to handle as the uniﬁed memory required for advanced SoC because it needs the simple control sensing operation for memory compiler, higher cell efﬁciency, and lower voltage operation for dynamic frequency and voltage control. Enhanced TTRAM (ET /50RAM) applies the actively body-bias control technique to realize the low voltage array operation, and never require the negative voltage source. The ET2RAM can realize both 263 MHz at 0.8 V and 10.2 mW at 0.5 V random-cycle operation, higher cell efﬁciency, and process scalability. It also provides the simple control method suitable for the uniﬁed macro for system-level power management SoC with keeping the merits of TTRAM as CMOS compatibility.