← 返回 JSSC 论文列表JSSC 2007第4期Data Converters0.25μmCMOS Image Sensor
A High-Speed, High-Sensitivity Digital CMOS Image Sensor With a Global Shutter and 12-bit Column-Parallel Cyclic A/D Converters
一款具有全局快门和高速高灵敏度的512x512 CMOS图像传感器
3500帧/秒, 19.9 V/lx·s灵敏度, 60dB动态范围
CMOS图像传感器全局快门列并行ADC高灵敏度高速成像
▸创新点1：列并行循环12位ADC（方法创新） - 该论文采用列并行循环12位ADC架构，显著提高了图像传感器的读取速度和分辨率。通过在每个列中集成ADC，减少了信号传输路径，实现了高达3500帧/秒的全帧率，同时保持了12位的高分辨率。
▸创新点2：像素内电荷放大器（电路创新） - 在像素内集成电荷放大器，提高了电荷到电压的转换增益，从而增强了传感器的光学灵敏度（19.9 V/lx·s）。这种设计即使在大型光电二极管的情况下也能保持高灵敏度，同时降低了噪声水平（1.8 mV）。
▸创新点3：可变时钟加速转换技术（方法创新） - 通过开发可变时钟和采样电容技术，显著提高了ADC的转换速度。这种技术优化了时钟频率和电容配置，使得高速数据采集成为可能，进一步支持了高帧率操作。
▸创新点4：全局电子快门与固定模式噪声消除（系统创新） - 采用全局电子快门和双采样保持阶段设计，有效消除了固定模式噪声（FPN），提高了图像质量。这种设计在高速和高灵敏度条件下仍能保持优异的动态范围（60 dB）。
Abstract
This paper presents a high-speed, high-sensitivity 512 512 CMOS image sensor with column parallel cyclic 12-bit ADCs and a global electronic shutter. Each pixel has a charge am- plifier for high charge-to-voltage conversion gain despite of using a large-size photodiode, and two sample-and-hold stages for the global shutter and fixed pattern noise (FPN) canceling. High-speed column-parallel cyclic ADC arrays with 12-bit resolution having a small layout size of 0.09 mm /50are integrated at both sides of image array. A technique for accelerating the conversion speed using variable clocking and sampling capacitance is developed. A digital gain control function using 14-bit temporal digital code is also set in the column parallel ADC. The fabricated chip in 0.25- m CMOS image sensor technology achieves the full frame rate in excess of 3500 frames/s. The in-pixel charge amplifier achieves the optical sensitivity of 19.9 V/lx s. The signal full scale at the pixel output is 1.8 V at 3.3-V supply and the noise level is measured to be 1.8 mV /114/109/115, and the resulting signal dynamic range is 60 dB.