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A Low-Power Low-V oltage 10-bit 100-MSample/s Pipeline A/D Converter Using Capacitance
提出一种采用电容耦合技术的低功耗低压10位100MS/s流水线ADC
10-bit, 100MS/s, 55.3dB SNDR, 71.5dB SFDR, 33mW
低功耗低压流水线ADC电容耦合CMOS
▸电容耦合采样保持级实现1.0V电源电压下的高SFDR
▸电容耦合折叠共源共栅放大器有效降低增益级功耗
▸90nm CMOS工艺实现低功耗设计
Abstract
This paper presents a low-power low-voltage 10-bit 100-MSample/s pipeline analog-to-digital converter (ADC) using capacitance coupling techniques. A capacitance coupling sample- and-hold stage achieves high SFDR with 1.0-V supply voltage at a high sampling rate. A capacitance coupling folded-cascode ampli- fier effectively saves the power consumption of the gain stages of the ADC in a 90-nm digital CMOS technology. The SNDR and the SFDR are 55.3 dB and 71.5 dB, respectively, and the power con- sumption is 33 mW.