JSSC 2007第4期Clocking & PLLs0.13μmPLLVCO

An On-chip Calibration Technique for Reducing Supply V oltage Sensitivity in

提出一种片上校准技术，降低环形振荡器对电源电压的敏感性。

1-V 0.13-μm CMOS, 0.5 to 2 GHz, 3.95 ps rms jitter at 1.4 GHz

片上校准环形振荡器电源电压敏感性PLLCMOS

▸创新点1：片上校准技术（方法创新）- 提出了一种新型的片上校准技术，通过实时调整环形振荡器的参数，显著降低了电源电压波动对振荡器频率的影响，提升了系统的稳定性。

▸创新点2：降低电源电压敏感性（电路创新）- 设计了独特的电路结构，结合片上校准技术，有效减少了电源电压变化对环形振荡器性能的敏感性，使得系统在0.5至2 GHz的工作频率范围内表现出更强的鲁棒性。

▸创新点3：鲁棒性能对抗VCO电源噪声（系统创新）- 通过集成片上校准电路，系统在1 MHz和10 MHz的VCO电源噪声下，均表现出显著的性能提升，rms抖动分别从8.22 ps和16.8 ps降低至3.95 ps和3.97 ps，大幅提升了系统的抗噪声能力。

▸创新点4：低功耗与小面积（系统创新）- 在1.4 GHz工作频率下，整个PLL系统的总功耗仅为9.6 mW，且PLL核心与校准电路的芯片面积总和仅为0.064 mm²，实现了高性能与低功耗、小面积的平衡。

Abstract

A technique for reducing the supply voltage sensitivity of a ring oscillator using on-chip calibration is described. A 1-V 0.13- m CMOS PLL demonstrates robust performance against VCO supply noise over operating frequencies of 0.5 to 2 GHz. In the presence of a 10-mV 1-MHz VCO supply noise, the measured rms jitter of the proposed PLL with on-chip calibration is 3.95 ps at a 1.4-GHz operating frequency, while a conventional design mea- sures 8.22 ps rms jitter. For 10-MHz VCO supply noise, the mea- sured rms jitter is improved from 16.8 ps to 3.97 ps. The total power consumption of the PLL is 9.6 mW at 1.4 GHz, and the combined core die area of the PLL and the calibration circuitry is 0.064 mm /50.