An SRAM Design in 65-nm Technology Node Featuring Read and Write-Assist Circuits to Expand Operating V oltage Harold Pilo, Charlie Barwin, Geordie Braceras, Chris Browning, Steve Lamphier, and

Abstract

This paper describes a 32-Mb SRAM that has been designed and fabricated in a 65-nm low-power CMOS Technology. The 62-mm /50die features read-assist and write-assist circuit tech- niques that expand the operating voltage range and improve manufacturability across technology platforms. Hardware mea- surements demonstrate the fail-count improvements achieved by integrating these techniques. The decrease in fail-count provides a 100-mV improvement of VDD /77/73/78during the read operation. Write operations are also improved, especially with weak NFET cell transistors. The circuit techniques have been replicated on a 72-Mb stand-alone standard SRAM product where the area over- head from the additional circuits is approximately 4%. The 32-Mb SRAM has also been successfully migrated to other yield-learning SRAMs in 45-nm bulk and SOI technologies with minimum circuit changes.