JSSC 2007第5期Wireline I/O0.18μm

A 10-Gb/s Inductorless CMOS Limiting Ampliﬁer With Third-Order Interleaving

一种采用三阶交织有源反馈的无电感CMOS限幅放大器，适用于10Gb/s宽带应用。

0.18μm CMOS, 1.8V, 189mW, 42dB增益, 9GHz带宽, 10Gb/s速率

限幅放大器CMOS无电感交织反馈宽带

▸创新点1：无电感设计 - 采用无电感电路技术，避免了传统设计中螺旋电感带来的面积和性能限制，在0.18μm CMOS工艺下实现0.68×0.8 mm²的紧凑芯片尺寸，同时降低了工艺复杂度。

▸创新点2：三阶交织有源反馈 - 通过创新的三阶交织有源反馈结构，有效提升了电路的带宽至9 GHz，同时抑制了频带内的增益峰值，解决了高速放大器中带宽与稳定性之间的矛盾。

▸创新点3：带宽增强与增益峰值抑制的协同优化 - 在无电感设计基础上，通过独特的反馈网络设计，实现了42 dB高增益与9 GHz宽带的协同优化，输入灵敏度达10 mV（BER=10⁻¹²），适用于10 Gb/s高速应用。

▸创新点4：低功耗高性能平衡 - 在1.8V电源电压下仅消耗189 mW功耗，同时达成300 mV输出摆幅和10 mV输入灵敏度，展现了功率效率与高速性能的突破性平衡。

Abstract

This paper presents an inductorless circuit technique for CMOS limiting ampliﬁers. By employing the third-order in- terleaving active feedback, the bandwidth of the proposed circuit can be effectively enhanced while maintaining a suppressed gain peaking within the frequency band. Using a standard 0.18- m CMOS process, the limiting ampliﬁer is implemented for 10-Gb/s broadband applications. Consuming a DC power of 189 mW from a 1.8-V supply voltage, the fabricated circuit exhibits a voltage gain of 42 dB and a 3-dB bandwidth of 9 GHz. With a2 /51/49 1 pseudo-random bit sequence at 10 Gb/s, the measured output swing and input sensitivity for a bit-error rate of 10 /49/50are 300 and 10 mV /112/112, respectively. Due to the absence of the spiral inductors, the chip size of the limiting ampliﬁer including the pads is 0.68 0.8 mm/50where the active circuit area only occupies 0.32 0.6 mm/50.