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JSSC 2007第5期Clocking & PLLs0.13微米VCOClock Generation

A Fully Integrated 0.13-/22m CMOS Digital Low-IF DBS Satellite Tuner Using a Ring Oscillator-Based

采用0.13微米CMOS工艺实现的全集成低中频DBS卫星调谐器
90 dB增益范围, 10 dB噪声系数, 0.5-W功耗, 1.8/3.3-V双电源
CMOS卫星调谐器低中频环形振荡器全集成
创新点1:基于环形振荡器的宽带频率合成器(方法创新) - 采用宽频带环形振荡器实现大频率步进的频率合成,显著降低了相位噪声和功耗,同时支持单芯片集成,具体指标包括1.3° rms集成相位噪声和50 dBc的杂散抑制。
创新点2:数字域二次下变频技术(系统创新) - 通过首次下变频至滑动低中频后,在数字域完成二次下变频至基带,提高了系统灵活性和抗干扰能力,同时简化了模拟电路设计。
创新点3:无电感设计减少寄生耦合(电路创新) - 通过消除电感和使用小面积环形振荡器,有效减少了寄生磁性和衬底耦合,实现了敏感调谐器和噪声数字解调器的单芯片集成,die面积仅为1.8×1.2 mm²。
创新点4:离散步进AGC环路与数字校准技术(电路创新) - 采用离散步进AGC环路降低了噪声系数并提高了线性度,同时利用复制环形振荡器实现自动信号路径增益和带宽数字校准,优化了系统性能。
Abstract
A low-IF fully integrated tuner for DBS satellite TV applications has been realized in 0.13- m CMOS. A wideband ring oscillator-based frequency synthesizer having a large frequency step was used to downconvert a cluster of channels to a sliding low-IF frequency, while the second downconversion to baseband was performed in the digital domain. Eliminating the inductors and using a small-area oscillator has reduced both the parasitic magnetic and substrate coupling, allowing single-chip integration of the sensitive tuner and the noisy digital demodulator. A sig- nificant reduction in die area was achieved by using a single os- cillator to cover the entire satellite TV spectrum, while a noise attenuator was cascaded with the PLL passive loop filter to re- duce the equivalent VCO tuning gain. This improves PLL noise and spur performance and allows the on-chip integration of the loop filter. The digital low-IF tuner allows the use of a discrete step AGC loop that results in lower noise figure and higher lin- earity. Automatic signal path gain and bandwidth digital calibra- tion was realized using replica ring oscillators. Tuner specifications include: 90 dB gain range, 10 dB noise figure at max gain, /4325 dBm IIP3 at min gain, 1.3 rms integrated phase noise, 50 dBc spurs, 0.5-W power consumption from dual 1.8/3.3-V supplies, and 1.8 1.2 mm/50die area.