A Multilevel Read and Verifying Scheme for Bi-NAND

Abstract

A multilevel sensing and read verifying circuit is proposed for Bi-NAND (Buried bit-line NAND) type flash memo- ries. The Bi-NAND technology employs the negative programmed threshold voltage to facilitate the multilevel storage with lower program/erase bias and programming disturbance. The sensing circuit utilizes an advanced cross-coupled sense amplifier to achieve excellent immunity against mismatch effect and reduc- tion of power consumption. As well, it acts as data latch during multilevel sensing and verifying operations. By comparing to the conventional and simultaneous verifying circuits, the proposed scheme with dichotomous architecture simplifies the verifying circuit and speeds up verification process for multilevel operation. By adding only one latch and a pair of switches, the circuit can be easily expanded for one more bit per cell.