Algorithmic Design of CMOS LNAs and PAs for 60-GHz Radio

Abstract

Sixty-gigahertz power (PA) and low-noise (LNA) amplifiers have been implemented, based on algorithmic de- sign methodologies for mm-wave CMOS amplifiers, in a 90-nm RF-CMOS process with thick 9-metal-layer Cu backend and transistor /84 /77/65/88of 120 GHz/200 GHz. The PA, fabricated for the first time in CMOS at 60 GHz, operates from a 1.5-V supply with 5.2 dB power gain, a 3-dB bandwidth 13 GHz, a /80/49/100/66of /436.4 dBm with 7% PAE and a saturated output power of /439.3 dBm at 60 GHz. The LNA represents the first 90-nm CMOS implementation at 60 GHz and demonstrates improvements in noise, gain and power dissipation compared to earlier 60-GHz LNAs in 160-GHz SiGe HBT and 0.13- m CMOS technologies. It features 14.6 dB gain, an /73/73/80/51of 6.8 dBm, and a noise figure lower than 5.5 dB, while drawing 16 mA from a 1.5-V supply. The use of spiral inductors for on-chip matching results in highly compact layouts, with the total PA and LNA die areas with pads measuring /48 /51/53 /48 /52/51mm/50and /48 /51/53 /48 /52/48mm/50, respectively.