← 返回 JSSC 论文列表
📄 下载 JSSC 原文 PDF
JSSC 2007第5期Other0.25μmESD

Implementation of Initial-On ESD Protection Concept With PMOS-Triggered SCR Devices in Deep-Submicron CMOS Technology

提出一种具有初始导通功能的PMOS触发SCR设计,用于深亚微米CMOS技术的ESD保护。
2.5V VDD操作电压
ESD保护SCR器件深亚微米CMOS初始导通PMOS触发
创新点1:初始导通功能(方法创新) - 提出了一种新型SCR设计,具备初始导通功能,显著降低了触发电压并提高了导通效率,适用于深亚微米CMOS技术的ESD保护,无需特殊器件或工艺修改。
创新点2:PMOS触发SCR(电路创新) - 采用PMOS触发SCR器件,实现了在通用CMOS工艺中的ESD保护设计,避免了使用特殊原生器件,简化了制造流程并降低了成本。
创新点3:高保持电压设计(系统创新) - 设计了具有足够高保持电压的SCR器件,有效避免了在2.5V VDD工作电压下的闩锁问题,提升了系统的可靠性和稳定性。
创新点4:工艺兼容性验证(方法创新) - 在完全硅化的0.25微米CMOS工艺中成功验证了新型初始导通ESD保护设计的可行性,证明了其在实际应用中的广泛适用性和可制造性。
Abstract
In order to enhance the applications of SCR devices for deep-submicron CMOS technology, a novel SCR design with “initial-on” function is proposed to achieve the lowest trigger voltage and the highest turn-on efficiency of SCR device for effective on-chip ESD protection. Without using the special na- tive device (NMOS with almost zero or even negative threshold voltage) or any process modification, this initial-on SCR design is implemented by PMOS-triggered SCR device, which can be realized in general CMOS processes. This initial-on SCR design has a high enough holding voltage to avoid latchup issues in a VDD operation voltage of 2.5 V. The new proposed initial-on ESD protection design with PMOS-triggered SCR device has been successfully verified in a fully-silicided 0.25- m CMOS process.