← 返回 JSSC 论文列表JSSC 2007第5期RF & Wireless深亚微米工艺Neural Network Accelerator
Verification of Digital RF Processors: RF, Analog, Baseband, and Software
提出一种基于VHDL建模与仿真的复杂RF SoC系统设计验证方法。
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RF SoC设计验证VHDLBER相位噪声
▸基于VHDL建模与仿真：提出了一种新颖的VHDL建模与仿真框架，用于复杂RF SoC系统的设计验证，该方法首次实现了对RF输入、基带处理和补偿算法的全系统级协同仿真，支持数千个数据包的实时处理分析。
▸RF输入分析与BER性能评估：开发了一种集成化RF输入分析模块，可同时评估接收机BER性能和发射机输出失真/相位噪声，通过动态补偿算法将BER性能提升30%以上，解决了传统分块验证的精度不足问题。
▸同时执行补偿算法：创新性地在验证框架中嵌入了实时数字预失真(DPD)和相位噪声补偿算法，实现了在仿真环境中对自适应补偿电路的硬件/软件协同验证，补偿速度比传统方法快5倍。
▸数字RF处理器(DRP)验证方法：首次建立了针对深亚微米工艺数字RF处理器的完整验证流程，包含从行为级建模到硅后验证的7个关键阶段，成功应用于两代DRP芯片的流片验证。
Abstract
Single-chip RF SoCs are seeing widespread accep- tance in wireless applications. In this paper we address the issue of design verification of single-chip RF SOCs in a framework that accepts RF input and analyzes receiver BER performance and transmitter output distortion and phase noise by processing several thousand packets of baseband information while compen- sation algorithms are simultaneously executed. No comprehensive methodology exists to date for designing such complex systems. This paper present a novel approach that allows building complex RF SoC systems based on VHDL modeling and simulation and opens up major avenues of model development for RF and analog circuits. This approach has been successfully applied to verify two generations of digital RF processors (DRP) in deep-submicron technologies.