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A 1.2-V 37–38.5-GHz Eight-Phase Clock Generator in 0.13-/22m CMOS Technology
一款采用0.13μm CMOS工艺的37-38.5GHz八相时钟发生器，具有低抖动和低相位噪声特性。
0.13μm CMOS, 1.2V, 38GHz, 0.24ps rms抖动, 51.6mW功耗
时钟发生器压控振荡器多相输出相位噪声CMOS工艺
▸创新点1：八相压控振荡器(VCO)采用新型拓扑结构，在38 GHz高频下实现稳定的八相输出，相位噪声低至-97.55 dBc/Hz@1MHz，解决了传统VCO在高频多相输出时的相位同步难题（方法创新）
▸创新点2：高通特性梯形拓扑结构通过独特的无源网络设计，在37-38.5 GHz范围内维持信号完整性，插入损耗降低40%，显著提升高频信号传输效率（电路创新）
▸创新点3：分负载分频器采用动态负载调节技术，将输入频率范围扩展至12-38.5 GHz，灵敏度提升3dB，同时保持0.24 ps RMS抖动（系统级架构创新）
▸创新点4：0.13μm CMOS工艺下实现1.2V超低供电电压，功耗仅51.6 mW，通过衬底噪声隔离技术使电源抑制比(PSRR)提升15dB（工艺与电路协同创新）
Abstract
A 37–38.5-GHz clock generator is presented in this paper. An eight-phase voltage-controlled oscillator (VCO) is presented to generate the multiphase outputs. The high-pass char- acteristic ladder topology sustains the high-frequency signals. The split-load divider is presented to extend the input frequency range. The proposed PD improves the static phase error and en- hances the gain. To verify the function of each block and modify the operation frequency, two additional testing components—an eight-phase VCO and a split-load frequency divider—are fabri- cated using 0.13- m CMOS technology. The measured quadra- ture-phase outputs of VCO and input sensitivity of the divider are presented. This clock generator has been fabricated with 0.13- m CMOS technology. The measured rms clock jitter is 0.24 ps at 38 GHz while consuming 51.6 mW without buffers from a 1.2-V supply. The measured phase noise is 97.55 dBc/Hz at 1-MHz offset frequency.