← 返回 JSSC 论文列表JSSC 2007第6期RF & Wireless0.18μmVCO
A 1.5 V 3.1 GHz–8 GHz CMOS Synthesizer for 9-Band MB-OFDM UWB Transceivers
设计用于9频段MB-OFDM UWB收发器的15V 31GHz CMOS合成器。
1.5V, 127.4 dBc/Hz @10MHz, 4.43°, <22 dBc, <1ns, 59mA
CMOS合成器MB-OFDMUWB宽带混频器正交VCO
▸创新点1：宽带单边带混频器采用宽带感性网络负载技术，显著提升混频器的带宽和线性度，支持3.1 GHz至8.0 GHz的超宽带频率覆盖，同时优化了相位噪声性能。
▸创新点2：改进的变压器耦合正交VCO通过优化变压器结构和耦合机制，实现了更低的相位噪声（127.4 dBc/Hz @10 MHz偏移）和更高的频率稳定性，适用于多频段OFDM系统。
▸创新点3：互连负载不敏感布局技术通过创新的布线设计和负载隔离方法，减少了互连寄生效应，提升了电路的整体性能，特别是在高频（31 GHz）下的信号完整性。
▸创新点4：双转换零中频架构的系统创新，结合上述电路技术，实现了快速切换（<1 ns）和低功耗（59 mA @1.5 V），适用于多频段UWB通信。
Abstract
This paper presents the design of a CMOS synthesizer for dual-conversion zero-IF2 Multi-Band OFDM (MB-OFDM) transceivers covering the first 9 frequency bands from 3.1 GHz to 8.0 GHz, each with a bandwidth of 528 MHz. A wideband single-sideband mixer with wideband inductive network loading is proposed. Moreover, a modified transformer-coupled quadrature VCO and interconnection-loading-insensitive layout technique are employed. Fabricated in TSMC 0.18- m CMOS process and operated at 1.5 V , the synthesizer measures phase noise of 127.4 dBc/Hz at 10 MHz offset, integrated phase noise of 4.43 , sideband suppression of better than 22 dBc, and a switching time of less than 1ns while consuming 59 mA.