← 返回 JSSC 论文列表JSSC 2007第6期Digital Circuits0.18μmDelta-Sigma ADCNeural Network Accelerator
A Power-Efficient Two-Channel Time-Interleaved /6/1Modulator for
一种高效能双通道时间交织二阶ΣΔ调制器，适用于宽带应用。
0.18μm CMOS, 1.8V, 132MHz, 85dB动态范围, 5.4mW功耗
ΣΔ调制器时间交织宽带应用低功耗CMOS
▸创新点1：采用单积分器通道架构，显著减少有源元件数量，仅需两个运算放大器即可实现整个调制器，降低了功耗和面积（功耗5.4 mW，面积1.1 mm²）。
▸创新点2：直接利用积分器输出作为量化器输入，省去了传统设计中额外的量化器输入生成电路，简化了系统结构并提高了信号处理效率。
▸创新点3：提出的双通道时间交织架构对通道失配效应具有鲁棒性，确保了在宽带应用（如ADSL）中的稳定性和性能（动态范围85 dB，带宽1.1 MHz）。
▸创新点4：采用简单的时钟方案，降低了系统复杂度，同时支持高达132 MHz的有效时钟频率，适用于高速宽带应用。
Abstract
A two-channel time-interleaved second-order sigma-delta modulator for broadband applications including asymmetrical digital subscriber line (ADSL) is presented. The proposed two-channel /6/1 modulator uses a single integrator channel which does not require additional active elements for the quantizer input generation, since the integrator outputs are directly used as the input of the quantizers. As a result, the entire modulator can be implemented using only two op-amps, which is beneficial for both power consumption and area. Furthermore, this architecture is robust to channel mismatch effects and can operate with a simple clocking scheme. The /6/1 modulator achieves a dynamic range of 85 dB over a 1.1-MHz signal band- width with an effective clock frequency of 132 MHz. The circuit is implemented in 0.18- m CMOS technology using metal–insu- lator–metal capacitors. The total power consumption of the /6/1 modulator is 5.4 mW from a 1.8-V supply and occupies an active area of 1.1 mm /50.