← 返回 JSSC 论文列表JSSC 2007第6期RF & Wireless0.18μm
A Receiver Architecture for Dual-Antenna Systems
提出一种低中频接收器架构，通过将双天线信号转换为复域正负频率，减少基带模数转换器数量。
0.18μm CMOS, 1.8V, 60.2mW, -55/-50dBm灵敏度, 50/53dB EVM
双天线系统低中频接收器复域信号处理CMOS技术灵敏度
▸创新点1：双天线信号复域正负频率转换（方法创新）。通过将两个天线接收的信号分别转换到复域的正负频率，实现了信号的有效分离和处理，减少了信号干扰，提高了接收效率。
▸创新点2：减少基带A/D转换器数量（电路创新）。通过复域正负频率转换技术，将原本需要两个基带A/D转换器的设计减少为一个，降低了硬件复杂度和成本，同时保持了信号处理的高效性。
▸创新点3：低中频接收器架构设计（系统创新）。采用低中频架构，有效避免了传统高IF架构中的干扰问题，提高了接收器的灵敏度和信号处理能力，具体表现为64 QAM信号下的EVM达到50/53dB。
▸创新点4：双接收器原型设计与实现（系统创新）。在0.18μm CMOS技术下设计和制造的双接收器原型，实现了55/50dBm的灵敏度和60.2 mW的低功耗，展示了该架构在实际应用中的高效性和可行性。
Abstract
The signals received by two antennas can be processed by a single time-shared receiver but only in the absence of inter- ferers and channel-select filters. A low-IF receiver architecture is introduced that translates two antenna signals to positive and negative frequencies in the complex domain, reducing the number of baseband A/D converters by a factor of two. A dual-receiver prototype designed and fabricated in 0.18- m CMOS technology provides a sensitivity of /55/50dBm with an EVM of /50/53dB for 64 QAM signals while drawing 60.2 mW from a 1.8-V supply.