JSSC 2007第6期Memory0.18-m CMOS

An Embeddable Multilevel-Cell Solid Electrolyte

基于固体电解质的非易失性存储器阵列，支持多级存储和低功耗操作。

437-ns cycle time, sub-40-ns access times, 10-A reference current

非易失性存储器固体电解质多级存储低功耗CMOS工艺

▸创新点1：低电压和低电流操作（方法创新）。该论文通过优化固体电解质材料的电化学特性，实现了在低于传统非易失性存储器的操作电压（具体数值未提及）和10μA参考电流下的稳定工作，显著降低了功耗。

▸创新点2：与常规CMOS工艺兼容（工艺创新）。仅需最少量额外掩模层（具体层数未说明），即可将固体电解质存储单元嵌入标准0.18μm CMOS工艺，解决了异质集成中的制造兼容性问题。

▸创新点3：多级存储能力（电路创新）。通过精密设计的读取电路和437ns周期控制，在单个存储单元实现2比特MLC存储，存储密度提升100%的同时保持亚40ns访问速度。

▸创新点4：嵌入式测试平台设计（系统创新）。集成1024个单元的2kb测试阵列，提供可扩展架构验证方案，支持快速参数调试与可靠性评估

Abstract

Nonvolatile memory cells based on solid electrolytes have many desirable attributes, including low-voltage and low-cur- rent operation and a simple process that allows them to be in- tegrated with conventional CMOS processes with minimal addi- tional masking layers. In this paper, we present a 2-kb memory block/testbed (1024 elements) using solid electrolyte cells. The com- pact memory design addresses many of the unusual operational is- sues associated with the solid electrolyte elements and allows for two digital bits to be stored and read from each cell with minimal circuitry. The design was fabricated in 0.18- m CMOS technology and the simulation and physical data are presented. Multilevel-cell (MLC) operation was demonstrated for a 10- A reference current with a 437-ns cycle time and sub-40-ns access times.