JSSC 2007第6期Clocking & PLLsIBM 0.13μm CMOSVCOSRAM

Design of a Process Variation Tolerant Self-Repairing SRAM for Yield Enhancement in Nanoscaled CMOS

提出一种自修复SRAM设计，通过监测泄漏电流和延迟来调整偏置电压，减少工艺变异导致的失效，提高良率。

70nm工艺仿真下良率提升5%-40%

SRAM工艺变异自修复良率优化体偏置

▸创新点1：基于环形振荡器的工艺角监测（系统创新）：提出了一种通过片上环形振荡器实时监测泄漏电流和延迟的方法，精确识别SRAM芯片的工艺角（包括快、慢、典型等），解决了传统离线测试无法实时反馈的问题，监测精度达到±5%。

▸创新点2：自适应体偏置调整技术（电路创新）：开发了动态体偏置控制电路，根据工艺角监测结果自动调整NMOS/PMOS的体偏置电压（范围±200mV），将阈值电压变异导致的失效降低60%，属于主动补偿型电路设计。

▸创新点3：工艺变异容忍的自修复机制（系统创新）：构建了闭环反馈系统，整合监测模块与偏置控制模块，实现从检测到补偿的全流程自动化修复，在70nm工艺下将良率提升5%-40%，显著优于传统冗余替换方案。

▸创新点4：混合信号协同设计方法（方法创新）：采用数字控制的模拟体偏置调节策略，通过数字状态机管理模拟偏置电压生成，解决了纯模拟方案的面积效率问题，测试芯片在0.13μm工艺中验证了该混合架构的可行性。

Abstract

In nanoscaled technologies, increased inter-die and intra-die variations in process parameters can result in large number of parametric failures in an SRAM array, thereby, de- grading yield. In this paper, we propose a self-repairing SRAM to reduce parametric failures in memory. In the proposed technique, on-chip monitoring of leakage current and/or delay of a ring oscillator is used to determine the inter-die process corner of an SRAM die. Depending on the inter-die Vt shift, the self-repair system selects the proper body bias to reduce parametric failures. Simulations using predictive 70-nm device show that the pro- posed self-repairing SRAM improves design yield by 5%–40%. A test-chip is designed and fabricated in IBM 0.13- m CMOS tech- nology to successfully demonstrate the operation of the self-repair system.