← 返回 JSSC 论文列表JSSC 2007第6期Power Management0.18-μm CMOS
Distributed Loss-Compensation Techniques for Energy-Efficient Low-Latency On-Chip Communication
通过分布式损耗补偿技术实现高效低延迟的片上互连
14-mm 3-Gb/s DDR link, 12.1 ps/mm latency, <2 pJ/b energy consumption
分布式损耗补偿负阻抗转换器低延迟高能效片上互连
▸创新点1：分布式损耗补偿技术（方法创新）：通过在片上互连线上定期插入负阻抗转换器（NICs），显著降低了信号传输损耗，从1 dB/mm降至0.3 dB/mm，提升了信号完整性。
▸创新点2：负阻抗转换器(NICs)的应用（电路创新）：NICs的引入有效补偿了片上互连线的损耗，实现了低功耗（<2 pJ/b）和低延迟（12.1 ps/mm）的高性能传输。
▸创新点3：片上传输线行为的近似实现（系统创新）：通过分布式损耗补偿技术，使得长距离片上互连线表现出接近理想传输线的特性，提升了数据传输速率（3 Gb/s）和可靠性（BER < 10^-12）。
▸创新点4：性能优化（系统创新）：相比传统RC线，功耗降低了三倍，延迟减少了一半，显著提升了片上互连的能效和速度。
Abstract
In this paper, we describe the use of distributed loss compensation to provide nearly transmission-line behavior for long on-chip interconnects. Negative impedance converters (NICs) inserted at regular intervals along an on-chip line are shown to reduce losses from more than 1 dB/mm to less than 0.3 dB/mm at 10 GHz. Results are presented for a 14-mm 3-Gb/s on-chip double-data-rate (DDR) link in 0.18- m CMOS technology, with a measured latency of 12.1 ps/mm and an energy consumption of less than 2 pJ/b with a BER /49/48 /49/52. This constitutes a factor-of-three improvement in power and a one-and-a-half-times improvement in latency over an optimally repeated RC line of the same wire width.