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A Low-Power Embedded SRAM for
介绍了一种新型超低功耗SRAM，通过四种新技术在面积、延迟和能耗间实现更好平衡，适用于无线应用。
0.18μm技术，8-KB SRAM，功耗降低2倍
超低功耗SRAM无线应用动态读取稳定性低摆幅写入
▸创新点1：更高效的内存数据总线（系统创新）。通过优化数据总线的结构和信号传输机制，减少了数据传输过程中的功耗和延迟，提升了整体能效，适用于低功耗无线应用场景。
▸创新点2：利用SRAM单元的动态读取稳定性（电路创新）。通过动态调整SRAM单元的读取稳定性，降低了读取操作时的功耗，同时保持了数据的可靠性，实现了功耗与性能的优化平衡。
▸创新点3：新的低摆幅写入技术（电路创新）。采用低摆幅信号进行写入操作，显著减少了写入过程中的能量消耗，同时确保了数据的正确写入，适用于低功耗嵌入式SRAM设计。
▸创新点4：分布式解码器（系统创新）。通过分布式解码器设计，减少了集中式解码带来的延迟和功耗，提升了SRAM的访问效率，适用于大规模存储器的低功耗优化。
Abstract
This paper introduces a novel ultra-low-power SRAM. A large power reduction is obtained by the use of four new techniques that allow for a wider and better trade-off be- tween area, delay and active and passive energy consumption for low-power embedded SRAMs. The design targets wireless applica- tions that require a moderate performance at an ultra-low-power consumption. The implemented design techniques consist of a more efficient memory databus, the exploitation of the dynamic read stability of SRAM cells, a new low-swing write technique and a distributed decoder. An 8-KB 5T SRAM was fabricated in a 0.18- m technology. The measurement results confirm the feasibility and the usefulness of the proposed techniques. A reduction of active power consumption with a factor of 2 is reported as compared to the current state of the art. The results are generalized towards a 32-KB SRAM.