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A Low Noise Figure 1.2-V CMOS GPS Receiver Integrated as a Part of a
本文探讨了在多模终端中集成GPS接收器的挑战，并提出了一种低噪声GPS接收器设计。
0.13μm CMOS, 1.2V, 49mW, 2.2dB噪声系数, -24dBm OOB IIP3
GPS接收器多模终端低噪声CMOS干扰环境
▸创新点1：集成GPS接收器到多模终端，通过最小化现有ASIC的修改实现了多模接收器的兼容性，显著降低了硬件复杂度和成本。该方法在0.13微米CMOS工艺下实现，展示了高度集成的系统级创新。
▸创新点2：低噪声设计，通过优化接收链路的噪声性能，实现了2.2 dB的极低噪声系数，提升了GPS接收器在干扰环境下的灵敏度。这一电路创新为高精度定位提供了关键技术支持。
▸创新点3：在1.2V低电压供电下实现49 mW的低功耗设计，同时保持高性能（如-4324 dBm的带外IIP3），展示了电源管理和电路优化的创新，适用于移动终端的长时续航需求。
▸创新点4：针对多无线电终端的干扰环境，提出了有效的抗干扰设计方案，通过系统级优化确保了GPS接收器在复杂电磁环境中的稳定性能，体现了系统架构的创新。
Abstract
This paper presents what kind of challenges are posed when a Global Positioning System (GPS) receiver is being added to a multiradio terminal. The GPS receiver chain is integrated as a part of a multiband and multimode receiver, designed for global system for mobile communications (GSM) and wideband code division multiple access (WCDMA). The hostile radio environment challenges in a terminal level are discussed. Especially, the modi- fications of the additional GPS mode to an existing receiver ASIC with minor and most necessary changes to the implementation is discussed and presented. The IC is implemented in a 0.13- m CMOS technology without any analog options. At 1.2-V supply voltage and total power dissipation of 49 mW for the analog signal path, the proposed GPS receiver features a noise figure of 2.2 dB and an out-of-band IIP3 of /4324 dBm for the worst-case test scenario, which makes it suitable to cellular handset usage in a demanding interference environment.