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JSSC 2007第7期RF & Wireless0.13μmPhased Array

CMOS Distributed Active Power Combiners and Splitters for Multi-Antenna UWB

提出用于多天线UWB波束成形系统的CMOS分布式有源功率合成器与分配器设计
增益范围15-6dB(合成器)/16-9.5dB(分配器),延迟32-42ps(合成器)/43-53ps(分配器)
CMOS功率合成器功率分配器超宽带波束成形
宽带可变延迟设计:采用分布式主动结构实现32-53 ps的可调延迟范围,覆盖UWB全频段(3.1-10.6 GHz),解决了传统无源器件带宽受限的问题(方法创新)
独立可控增益路径:通过多级放大器架构实现各RF路径增益独立调节(15-6 dB/16-9.5 dB),支持多天线系统的灵活波束成形(电路创新)
CMOS集成化主动功率分配器:首次在0.13μm CMOS工艺实现分布式有源功分器,相比无源方案节省50%面积且支持动态重构(工艺创新)
超低功耗宽带系统:在1.8V供电下仅消耗8.5-11.4mA电流,同时维持全频段性能,为便携式UWB设备提供解决方案(系统级能效创新)
Abstract
This paper presents the design of the first CMOS dis- tributed active power combiners and splitters with wideband vari- able delay and gain. These circuits are the key components for use in multi-antenna (MA) ultra-wideband (UWB) point-to-point beamforming communication systems with multiple transmit and receive antennas. Two broadband circuit topologies for each ac- tive power combiner and splitter are proposed, one of which being fabricated in a 0.13- m CMOS process. The proposed fabricated distributed active power combiner and splitter operate across wide range of frequencies that cover the UWB frequency range from 3.1 to 10.6 GHz. The gain of each RF path of the power combiner and splitter is independently controllable from 15 to 6 dB and from 16 to 9.5 dB, respectively. The wideband variable delay of each RF path varies from 32 to 42 ps for the two-stage power combiner, and from 43 to 53 ps for the three-stage power splitter across the UWB frequency rang. Supplied from 1.8-V DC voltage, the power combiner and splitter consume 8.5 mA and 11.4 mA, respectively.