JSSC 2007第7期RF & Wireless0.13μm

Flexible Baseband Analog Circuits for Software-Deﬁned Radio Front-Ends

提出一种用于软件定义无线电前端的数字可编程低通滤波器和可变增益放大器设计方法。

0.13μm CMOS, 1.2V, 0.35-23.5MHz可调频率, 85-163μVrms噪声, 0.72-21.6mW功耗

软件定义无线电低通滤波器可变增益放大器网络芯片自适应功耗

▸创新点1：数字可编程低通滤波器设计（电路创新） - 提出了一种新型数字可编程低通滤波器，通过数字控制实现截止频率在0.35 MHz至23.5 MHz范围内的连续可调，同时集成噪声水平自适应调整（85μVrms至163μVrms），显著提升了滤波器的灵活性和适应性。

▸创新点2：网络芯片驱动性能参数调节（系统创新） - 采用网络芯片（NoC）动态配置滤波器与放大器的关键参数（如截止频率、增益、噪声等），实现了实时性能优化，解决了传统模拟电路难以动态调整的难题。

▸创新点3：自适应功耗/性能平衡（方法创新） - 提出了一种动态功耗管理机制，根据性能需求自动调节电路功耗（LPF功耗从0.72 mW到21.6 mW可调），在保证性能的同时最大化能效比。

▸创新点4：两级可变增益放大器设计（电路创新） - 采用两级级联结构实现0 dB至39 dB的宽范围增益调节，并通过可重构带宽设计优化了不同增益下的频率响应，提升了SDR前端的信号处理能力。

Abstract

This paper presents a novel approach to design a digitally programmable low pass ﬁlter (LPF) and variable gain ampliﬁer (VGA) intended for a software-deﬁned radio (SDR) front-end. These ﬂexible analog circuits are driven by a net- work-on-chip (NoC) that is able to set performance parameters like cut-off frequency, selectivity, noise, and gain guaranteeing at any time a near-optimal power/perfomance trade-off. A design approach is proposed to tackle the challenges imposed by ﬂexi- bility in analog design. A silicon prototype is realized in 0.13- m CMOS technology with 1.2-V supply voltage to prove the validity of the proposed solution. The LPF provides a frequency tuning range between 0.35 MHz and 23.5 MHz with an adaptive inte- grated noise level between 85 Vrms and 163 Vrms whereby the power consumption conveniently varies from 0.72 mW to 21.6 mW according to the required performance. The VGA is made up of two cascaded gain stages and provides a gain range from about 0 dB to 39 dB with a reconﬁgurable power/bandwidth.