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70-GHz Effective Sampling Time-Base On-Chip Oscilloscope in CMOS
本文提出了一种基于CMOS工艺的70GHz有效采样时基片上示波器，采用欠采样和时域放大技术实现高效测量。
70-GHz采样率，4 mV电压分辨率，3.5 mW静态功耗
片上示波器欠采样时域放大CMOS高测量速度
▸创新点1：欠采样与时域放大技术结合（方法创新）。通过将欠采样技术与单路径时域放大处理相结合，实现了时间高效的嵌入式测量，有效提升系统带宽至70 GHz，同时保持4 mV的电压分辨率。
▸创新点2：高测量速度与低复杂度电路设计（系统创新）。采用简单电路组件（如标准CMOS工艺）实现高速测量，在0.18-μm工艺下仅需1.8V单电源供电，总功耗低至3.5 mW，面积仅0.45 mm²。
▸创新点3：片上自校准与测试集成（设计创新）。通过内置可编程串扰发生器和校准模块，实现最小化硅面积开销的快速校准，显著提升测试效率（如片上互联串扰的实时表征）。
▸创新点4：全CMOS兼容性（工艺创新）。在纯数字CMOS工艺中实现模拟高速测量功能，突破传统混合信号设计的限制，降低成本并提高可扩展性。
Abstract
This paper examines a time-base measurement system for on-chip digitization. Undersampling, combined with single-path time-domain amplification and processing, is used to perform the embedded measurement in a time-efficient manner. The proposed system relies on simple circuit components while performing high-speed measurements. Additionally, ease of calibration with minimal silicon area overhead renders the system attractive from a design-for-test perspective. The circuit was implemented in a 0.18- m standard digital CMOS process using a single 1.8-V supply. On-chip interconnect crosstalk generation with variable strength is included on chip for characterization, and successfully measured using the prototype chip. An effective 70-GHz sampling rate is experimentally obtained from the imple- mented on-chip oscilloscope, with a voltage resolution of 4 mV. The estimated static power dissipation is 3.5 mW, with a total active area of 0.45 mm /50taken up by the associated test and calibration vehicles.