← 返回 JSSC 论文列表JSSC 2007第8期RF & Wireless0.13μmNeural Network Accelerator
A 1.5-V 0.7–2.5-GHz CMOS Quadrature Demodulator for Multiband Direct-Conversion Receivers
一款集成正交解调器，采用0.13μm CMOS工艺，适用于多频段直接转换接收。
0.13μm CMOS, 1.5V, 20-24mA, 700MHz-2.5GHz, 35dB增益, 10dB NF
正交解调器CMOS多频段直接转换宽频带
▸创新点1：互补输入架构提高跨导（电路创新）。通过采用互补输入架构，在相同偏置电流下显著提高了跨导，从而增强了信号处理能力，优化了电路的增益和噪声性能。
▸创新点2：无电感设计（电路创新）。该设计避免了使用电感，简化了电路结构，降低了芯片面积和成本，同时保持了宽频带操作能力，适用于多频段直接转换接收器。
▸创新点3：宽频带操作能力（系统创新）。该解调器能够在700 MHz至2.5 GHz的宽频带范围内稳定工作，适应多种通信标准，提升了系统的灵活性和应用范围。
▸创新点4：高性能指标（系统创新）。该解调器在250 kHz中频带宽下实现了35 dB的转换电压增益，双边带噪声系数为10 dB，1/f噪声拐点为9-33 kHz，IIP3在0.1 MHz和1 MHz中频下分别为-34 dBm和-31 dBm，展示了优异的线性度和噪声性能。
Abstract
An integrated quadrature demodulator with an on-chip frequency divider is reported. The mixer consists of a transconductance stage, a passive current switching stage, and an operational amplifier output stage. A complementary input architecture has been used to increase the transconductance for a given bias current. The circuit is inductorless and is capable of operating over a broad frequency range. The chip was im- plemented in a 0.13- m CMOS technology. From 700 MHz to 2.5 GHz, the demodulator achieves 35 dB of conversion voltage gain with 250-kHz IF bandwidth, a double-sideband NF of 10 dB with 9–33 kHz 1/f-noise corner. The measured IIP3 is /434 dBm for a 0.1-MHz IF frequency and /4310 dBm for a 1-MHz IF frequency. The total chip draws 20 to 24 mA from a single 1.5-V supply.