JSSC 2007第8期Power Management0.13μmCharge PumpPLL

A 50-GHz Phase-Locked Loop in 0.13-/22m CMOS

0.13μm CMOS工艺下实现的50GHz锁相环，采用LC振荡器注入锁定分频器。

45.9-50.5GHz锁定范围，10dBm输出功率，57mW功耗，63.5/72/99 dBc/Hz相位噪声

锁相环LC振荡器注入锁定分频器CMOS相位噪声

▸采用LC振荡器注入锁定分频器

▸通过跟踪VCO和分频器的自振荡频率扩展工作频率范围

▸输出101GHz信号为硅集成电路技术锁定的最高频率

Abstract

A 50-GHz charge pump phase-locked loop (PLL) utilizing an LC-oscillator-based injection-locked frequency divider (ILFD) was fabricated in 0.13- m logic CMOS process. The PLL can be locked from 45.9 to 50.5 GHz and output power level is around 10 dBm. The operating frequency range is increased by tracking the self-oscillation frequencies of the voltage-controlled oscillator (VCO) and the frequency divider. The PLL including buffers consumes 57 mW from 1.5/0.8-V supplies. The phase noise at 50 kHz, 1 MHz, and 10 MHz offset from the carrier is 63.5, 72, and 99 dBc/Hz, respectively. The PLL also outputs second-order harmonics at frequencies between 91.8 and 101 GHz. The output frequency of 101 GHz is the highest for signals locked by a PLL fabricated using the silicon integrated circuits technology.