JSSC 2007第8期Clocking & PLLs0.18μmDLL

A DLL-Based Programmable Clock Multiplier in 0.18-/22m CMOS With 70 dBc

基于DLL的可编程时钟倍频器，采用0.18μm CMOS工艺，实现低抖动和低参考杂散。

150–400 MHz, 16 mW, 1–5 ps RMS jitter, 70 dBc reference spur level

时钟倍频器DLLCMOS相位抖动参考杂散

▸创新点1：采用循环DLL结构实现150-400 MHz宽范围可编程时钟倍频，通过动态延迟线复用技术显著降低功耗（16 mW）和面积开销，属于系统架构创新

▸创新点2：提出新型采样相位检测器技术，结合时间数字转换器(TDC)实现亚皮秒级精度（1-5 ps RMS抖动），解决了传统PLL中累积误差问题，属于电路级创新

▸创新点3：集成斩波稳定化和自动归零技术，通过动态失调消除将参考时钟串扰抑制至-70 dBc以下，属于噪声抑制方法创新

▸创新点4：采用混合信号校准技术，在0.18μm CMOS工艺下实现0.01%的占空比误差，通过数字辅助模拟电路提升量产一致性，属于工艺适配性创新

Abstract

This paper describes a 150–400 MHz programmable clock multiplier which uses a recirculating DLL. The clock mul- tiplier uses a sampling phase detector and employs chopping, autozeroing and various other circuit techniques to reduce static phase offset and crosstalk between the reference and the output clock. The DLL is implemented in 0.18- m CMOS, consumes 16 mW of power, and achieves 1–5 ps RMS jitter and 70 dBc reference spur level.