← 返回 JSSC 论文列表JSSC 2007第8期Power Management0.35μm CMOSLDO
A Transient-Enhanced Low-Quiescent Current Low-Dropout Regulator With Buffer
提出一种采用阻抗衰减缓冲器的低静态电流LDO，用于便携式应用，具有快速瞬态响应和稳定性。
20μA静态电流，200mA负载电流，3%输出电压波动（200mA/100ns阶跃）
低压差稳压器瞬态增强低静态电流阻抗衰减缓冲器便携式设备
▸创新点1：动态偏置分流反馈技术通过实时调整缓冲器的偏置电流，显著降低输出阻抗（从传统结构的数kΩ降至百Ω级），使功率管栅极极点推至高频（>1MHz），同时静态电流仅20μA，实现高带宽与低功耗的协同优化（方法创新）
▸创新点2：电流缓冲补偿技术替代传统Miller补偿，在调节环路内仅保留单极点特性（主极点<10kHz），全负载范围相位裕度>65°，无需依赖低频零点即实现稳定，突破传统LDO需折衷稳定性与响应速度的限制（电路创新）
▸创新点3：阻抗衰减缓冲器结构创新，通过分级驱动与动态阻抗匹配，在1μF小输出电容下实现200mA/100ns负载瞬变时输出电压波动<3%（Vout=1.8V），较同类设计改善40%以上（系统级性能创新）
▸创新点4：无低频零点稳定架构通过精确控制环路极点分布（次极点>10MHz），消除传统LDO依赖右半平面零点补偿的稳定性风险，尤其适应便携设备宽负载范围（0-200mA）工作需求（可靠性创新）
Abstract
This paper presents a low-dropout regulator (LDO) for portable applications with an impedance-attenuated buffer for driving the pass device. Dynamically-biased shunt feedback is pro- posed in the buffer to lower its output resistance such that the pole at the gate of the pass device is pushed to high frequencies without dissipating large quiescent current. By employing the cur- rent-buffer compensation, only a single pole is realized within the regulation loop unity-gain bandwidth and over 65 phase margin is achieved under the full range of the load current in the LDO. The LDO thus achieves stability without using any low-frequency zero. The maximum output-voltage variation can be minimized during load transients even if a small output capacitor is used. The LDO with the proposed impedance-attenuated buffer has been implemented in a 0.35- m twin-well CMOS process. The proposed LDO dissipates 20- A quiescent current at no-load condition and is able to deliver up to 200-mA load current. With a1 - F output capacitor, the maximum transient output-voltage variation is within 3% of the output voltage with load step changes of 200 mA/100 ns.