← 返回 JSSC 论文列表JSSC 2007第8期Data Converters0.18μm CMOSDAC
Low-Power Approaches to High-Speed Current-Steering Digital-to-Analog Converters in 0.18-/22m CMOS
论文探讨了在保持性能的同时降低电流舵数模转换器功耗的电路设计方法。
14-bit分辨率, 200MSPS转换率, 0.17mW/MSPS@1.8V, 0.28mW/MSPS@3.3V
低功耗电流舵DAC高速转换动态性能宽电压范围
▸创新点1：低功耗设计方法（电路创新）。通过优化电流源结构和开关控制策略，显著降低了功耗，实现了0.17 mW/MSPS的功耗/转换率指标，适用于1.8V供电。
▸创新点2：宽电源电压范围（系统创新）。采用兼容3.3V的器件设计，支持1.7V至3.6V的宽电源电压范围，增强了系统的灵活性和适应性。
▸创新点3：高动态性能（电路创新）。通过改进电流匹配和噪声抑制技术，在50MHz输出频率下实现了70dB的单音SFDR，以及在71MHz输出下75dBc的双音IMD，显著提升了动态性能。
▸创新点4：工艺兼容性（工艺创新）。基于0.18μm CMOS工艺的一层多晶四层金属（1P4M）技术，确保了设计的高集成度和低成本实现。
Abstract
This paper will discuss a number of circuit ap- proaches which lower the power consumed by a current steering digital-to-analog converter while maintaining both DC and AC performance levels. An example design provides 14-bit resolution and 200 MSPS conversion rate in a one-poly four-metal (1P4M) 0.18- m CMOS process. The inclusion of optional 3.3-V compat- ible devices allows operation over a supply range from 1.7 to 3.6 V. A power dissipation/conversion rate figure of merit of as low as 0.17 mW/MSPS was achieved for 1.8-V operation and as low as 0.28 mW/MSPS at 3.3 V. A measured single-tone SFDR of 70 dB is achieved at a 50-MHz output frequency, with a two-tone IMD of 75 dBc at 71 MHz output.