← 返回 JSSC 论文列表JSSC 2007第9期RF & Wireless0.25-m CMOS
A 0.2-mW 2-Mb/s Digital Transceiver Based on Wideband Signaling for Human
一种基于宽带信号的低功耗数字收发器，用于人体通信
2-Mb/s数据速率，0.2 mW功耗，1-V电源
人体通信低功耗数字收发器宽带信号时钟数据恢复
▸创新点1：采用宽带信号技术(WBS)实现高效人体通信，通过优化信道带宽（10 kHz至100 MHz）显著提升数据传输速率至2 Mb/s，同时保持低功耗（0.2 mW），属于系统级创新。
▸创新点2：直接耦合接口(DCI)设计通过50Ω/10Ω阻抗电极简化了人体信道耦合，降低了信号衰减和接口复杂度，属于接口电路创新。
▸创新点3：低电压数字控制振荡器（DCO）结合二次采样技术，在1V电源电压下实现高精度时钟恢复，功耗仅为0.02 mW，属于混合信号电路创新。
▸创新点4：全数字时钟数据恢复（CDR）电路摒弃传统模拟PLL，采用数字逻辑实现抗噪声同步，在1.1×10⁻⁴误码率下支持2 Mb/s速率，属于数字架构创新。
Abstract
This paper presents a low-power wideband signaling (WBS) digital transceiver for data transmission through a human body for body area network applications. The low-power and high- speed human body communication (HBC) utilizes a digital trans- ceiver chip based on WBS and adopts a direct-coupled interface (DCI) which uses an electrode of 50- /10impedance. The channel in- vestigation with the DCI identifies an optimum channel bandwidth of 10 kHz to 100 MHz. The WBS digital transceiver exploits a di- rect digital transmitter and an all-digital clock and data recovery (CDR) circuit. To further reduce power consumption, the proposed CDR circuit incorporates a low-voltage digitally-controlled oscil- lator and a quadratic sampling technique. The WBS digital trans- ceiver chip with a 0.25- m standard CMOS technology has 2-Mb/s data rate at a bit error rate of 1.1 /49/48 /55, dissipating only 0.2 mW from a 1-V supply generated by a 1.5-V battery.