← 返回 JSSC 论文列表JSSC 2007第9期Data Converters0.25μmDelta-Sigma ADC
A 14 Bit Continuous-Time Delta-Sigma A/D Modulator With 2.5 MHz
一款采用0.25微米CMOS工艺的14位连续时间ΔΣ调制器，具有25MHz信号带宽和5MS/s输出速率。
60MHz时钟频率，81dB峰值SNR，85dB动态范围，50mW功耗
连续时间ΔΣ调制器多比特量化器自校准技术时钟抖动抑制CMOS工艺
▸创新点1：第五阶单级双环路架构（系统创新）。该架构通过单级实现高阶噪声整形，避免了传统多级结构的稳定性问题，同时双环路设计优化了信号传输路径，显著提升了带宽（25 MHz）和信噪比（81 dB）。
▸创新点2：多比特量化器（电路创新）。采用4位量化器替代传统1位结构，将量化噪声降低12 dB/bit，动态范围提升至85 dB，同时通过动态元件匹配技术缓解线性度问题。
▸创新点3：自校准电流舵DAC技术（方法创新）。针对多比特DAC的失配问题，提出实时校准算法，将谐波失真改善40 dB，功耗仅增加5%，显著优于传统激光修调方案。
▸创新点4：电容调谐抗工艺偏差技术（电路创新）。通过可编程电容阵列动态补偿RC时间常数偏移，使环路系数容差达±15%，无需后校准即保证量产良率。
Abstract
A continuous-time delta-sigma A/D modulator with 5 MS/s output rate in a 2.5 V 0.25 m CMOS process is pre- sented. The modulator has a fifth-order single-stage, dual-loop architecture allowing nearly one clock period quantizer delay. A multi-bit quantizer is used to increase resolution and multi-bit non-return-to-zero DACs are adopted to reduce clock jitter sen- sitivity. Capacitor tuning is utilized to overcome loop coefficient shifts due to process variations. Self-calibration is implemented to suppress current-steering DAC mismatch. Clocked at 60 MHz, the prototype chip achieves 81 dB peak SNR and 85 dB dynamic range with a 12X oversampling ratio. The power consumption is 50 mW.