A 5–6 GHz 1-V CMOS Direct-Conversion Receiver With an Integrated Quadrature Coupler Hsiao-Chin Chen, Tao Wang, and Shey-Shi Lu

Abstract

This paper describes a novel monolithic low voltage (1-V) CMOS RF front-end architecture with an integrated quadra- ture coupler (QC) and two subharmonic mixers for direct-down conversion. TheLC-folded-cascode technique is adopted to achieve low-voltage operation while the subharmonic mixers in conjunc- tion with the QC are used to eliminate LO self-mixing. In addition, the inherent bandpass characteristic of the LC tanks helps sup- pression of LO leakage at RF port. The circuit was fabricated in a standard 0.18- m CMOS process for 5–6 GHz applications. At 5.4 GHz, the RF front-end exhibits a voltage gain of 26.2 dB and a noise figure of 5.2 dB while dissipating 45.5 mW from a 1.0-V supply. The achieved input-referred DC-offset due to LO self-mixing is below 110.7 dBm.