← 返回 JSSC 论文列表JSSC 2007第9期RF & Wireless0.13μmSAR ADCDAC
A Fully Integrated Auto-Calibrated Super- Regenerative Receiver in 0.13-/22m CMOS
设计了一种0.13μm CMOS工艺的2.4 GHz ISM频段超再生接收机，具有自动校准功能。
0.13μm CMOS, 2.4 GHz, 500 kb/s, 2.8 mW, 5.6 nJ/bit
超再生接收机CMOS2.4 GHz自动校准低功耗
▸创新点1：采用频率合成器调谐通带的方法创新，通过动态调整接收机的工作频率，实现了在2.4 GHz ISM频段的高效信号捕获，显著提升了接收机的频率适应性和抗干扰能力。
▸创新点2：引入SAR逻辑驱动电流DAC的电路创新，通过数字模拟转换器精确校准淬灭信号，优化了超再生接收机的选择性和灵敏度，使其在低功耗条件下仍能保持高性能。
▸创新点3：通过增强滤波器和超再生灵敏度的系统创新，结合自动校准技术，显著提升了接收机的信号处理能力，实现了90 dBm的高灵敏度和500 kb/s的数据传输速率。
▸创新点4：整体设计实现了高度集成化，芯片面积小于1 mm²，功耗仅为2.8 mW，能量效率达到5.6 nJ/bit，为低功耗短距离通信提供了高效的解决方案。
Abstract
Super-regeneration is re-examined for its simplicity and power efficiency for low-power, short-range communication. A fully integrated super-regenerative receiver in 0.13- m CMOS is designed to operate in the 2.4 GHz ISM band. A frequency synthesizer scheme tunes the passband. Successive approximation register (SAR) logic driving a current digital-to-analog converter (DAC) calibrates the quench signal to enhance the selectivity of a -enhanced filter and the sensitivity of super-regeneration. A single-chip prototype receiver occupies less than 1 mm /50, has a turn-on time of 83.6 s, a channel spacing of 10 MHz, and a sensitivity of 90 dBm. A data rate of 500 kb/s is achieved with a power consumption of 2.8 mW, corresponding to energy consumption of 5.6 nJ per received bit.