← 返回 JSSC 论文列表JSSC 2007第9期Image Sensors0.18μm
A Real-Time Image-Feature-Extraction and Vector-Generation VLSI Employing Arrayed-Shift-Register Architecture
开发了一种用于实时图像识别的特征提取和向量生成VLSI芯片，采用阵列移位寄存器架构和流水线方向边缘滤波电路。
0.18μm 5-metal CMOS, 9.7 ns/vector element, 6.1 frames/s VGA-size image
特征提取向量生成实时图像识别VLSI边缘滤波
▸创新点1：阵列移位寄存器架构（系统创新） - 该论文采用阵列式移位寄存器架构，实现了64x64像素识别窗口的逐像素扫描，显著提高了图像特征提取的并行处理能力，支持每64个时钟周期生成一个64维特征向量。
▸创新点2：流水线方向边缘滤波电路（电路创新） - 通过设计流水线化的方向边缘滤波电路，优化了图像边缘检测的实时性，结合自适应阈值技术，有效提升了特征提取的精度和速度。
▸创新点3：高速中值电路用于自适应阈值确定（方法创新） - 提出了一种基于混合信号原理的高精度多数表决电路，实现了二进制中值搜索算法，能够快速适应局部亮度变化，显著提高了边缘滤波的鲁棒性。
▸创新点4：高性能指标（系统创新） - 实验证明，该芯片在0.18微米CMOS工艺下实现了每特征向量元素小于9.7 ns的生成速度，支持VGA图像以6.1帧/秒的速率处理，比3 GHz通用处理器快10^51倍。
Abstract
A feature-extraction and vector-generation VLSI has been developed for real-time image recognition. An ar- rayed-shift-register architecture has been employed in conjunc- tion with a pipelined directional-edge-filtering circuitry. As a result, it has become possible to scan an image, pixel by pixel, with a 64 64-pixel recognition window and generate a 64-di- mensional feature vector in every 64 clock cycles. In order to determine the threshold for edge-filtering operation adaptive to local luminance variation, a high-speed median circuit has been developed. A binary median search algorithm has been imple- mented using high-precision majority voting circuits working in the mixed-signal principle. A prototype chip was designed and fabricated in a 0.18- m 5-metal CMOS technology. A high-speed feature vector generation in less than 9.7 ns/vector element has been experimentally demonstrated. It is possible to scan a VGA-size image at a rate of 6.1 frames/s, thus generating as many as 1.5 10/54feature vectors per second for recognition. This is more than 10/51times faster than software processing running on a 3-GHz general-purpose processor.