JSSC 2007第9期RF & Wireless0.18μm SiGeLNANeural Network Accelerator

Design and Analysis of a Performance-Optimized CMOS UWB Distributed LNA

设计并分析了一种性能优化的CMOS超宽带分布式低噪声放大器（DLNA），采用带宽增强型共源共栅单元。

噪声系数2.9 dB, 增益8 dB, IIP3 3.55 dBm, 功耗12 mA@1.8V

CMOS分布式低噪声放大器超宽带噪声优化共源共栅

▸创新点1：带宽增强型共源共栅单元设计（电路创新）。通过在共源和共栅器件之间引入电感，有效扩展了带宽，同时降低了高频输入参考噪声，提升了整体性能。

▸创新点2：系统噪声分析与优化（方法创新）。精确考虑了线端热噪声和所有CMOS共源共栅单元噪声源（包括闪烁噪声、相关栅极感应噪声和通道热噪声）对整体噪声系数的影响，实现了噪声的全面优化。

▸创新点3：多级性能优化架构（系统创新）。采用三级架构设计，结合带宽增强型共源共栅单元，实现了在7.5 GHz UWB频段内平坦的噪声系数（2.9 dB）和高增益（8 dB），同时保证了低回波损耗。

▸创新点4：低功耗设计（电路创新）。在0.18微米SiGe工艺下，仅使用MOS晶体管，实现了12 mA的低电流消耗和1.8V的低电压供电，提升了能效比。

Abstract

In this paper, the systematic design and analysis of a CMOS performance-optimized distributed low-noise ampliﬁer (DLNA) comprising bandwidth-enhanced cascode cells will be presented. Each cascode cell employs an inductor between the common-source and common-gate devices to enhance the band- width, while reducing the high-frequency input-referred noise. The noise analysis and optimization of the DLNA accurately ac- counts for the impact of thermal noise of line terminations and all device noise sources of each CMOS cascode cell including ﬂicker noise, correlated gate-induced noise and channel thermal noise on the overall noise ﬁgure. A three-stage performance-optimized wideband DLNA has been designed and fabricated in a 0.18- m SiGe process, where only MOS transistors were utilized. Measure- ments of the test chip show a ﬂat noise ﬁgure of 2.9 dB, a forward gain of 8 dB, and input and output return losses below 12 dB and 10 dB, respectively, across the 7.5 GHz UWB band. The circuit exhibits an average IIP3 of 3.55 dBm. The 872 m 872 m DLNA chip consumes 12 mA of current from a 1.8-V DC voltage.