A5 4d B/10+ 42 dB 10 Gb/s SiGe Transimpedance- Limiting Amplifier Using Bootstrap Photodiode Capacitance Neutralization and Vertical

Abstract

A high-gain 10 Gb/s transimpedance-limiting ampli- fier (TIA-LA) capable of directly driving a SERDES IC was re- alized in a 60 GHz 0.2 m SiGe BiCMOS SOI process. The shunt-feedback common-emitter input stage uses a bootstrap tech- nique to neutralize the photodiode parasitic capacitance. Cascode configurations and cross-coupled Miller capacitance cancellation were used to minimize the input capacitance of the signal path stages. This reduces the number of inter-stage isolation emitter- followers, allowing low-voltage operation. A signal-amplitude-de- pendent adjustable threshold was implemented in the back-end limiting stages by using inverse hyperbolic tangent circuits. Inte- grating the high-gain TIA-LA signal path on the same die was made possible by using an SOI process in conjunction with die thin- ning to reduce substrate coupling and minimizing the output-to- input bondwire magnetic coupling through a careful pin location selection. The main limiting-TIA IC specifications include: 96 dB /10 total gain given by 54 dB /10TIA gain and 42 dB LA voltage gain, 12 A input sensitivity, 8p A Hz input equivalent noise, 0.3 W power consumption from a 3.3 V supply and 1.8 1.8 mm/50die area.