← 返回 JSSC 论文列表JSSC 2007第9期Power Management65nmSRAM
On-Chip V oltage Down Converter to Improve SRAM Read/Write Margin and Static Power for Sub-Nano CMOS Technology Fang-shi Lai and Chia-Fu Lee
片上电压转换器提升SRAM读写裕度和静态功耗性能
0.7V操作电压，静态功耗改善5%
SRAM电压转换器静态功耗读写裕度65nm工艺
▸创新点1：基于VDC的动态电源供应方法，通过动态调整SRAM的供电电压，显著提高了读写裕度和静态功耗性能，尤其在高温环境下表现优异。
▸创新点2：可编程VDC优化读写裕度，允许独立调整读和写操作的电压裕度，从而大幅提升芯片的良率和可靠性。
▸创新点3：无需外部电源支持，VDC完全集成在芯片内部，简化了系统设计并降低了外部电源的依赖，适用于未来CMOS技术的SRAM设计。
▸创新点4：在0.7V低电压下稳定运行，通过VDC的支持，2M 65nm SRAM芯片能够在极低电压下工作，显著降低了功耗并提升了能效。
Abstract
VDC-based dynamic power supply approach has been demonstrated to effectively improve the read margin, write margin and static power dissipation for the sub-nano SRAM de- sign. The static power dissipation is found to be 5 improvement in the room and high temperatures while the chip is in the standby mode. The measured data indicate the excellent /86/99/99/109/105/110improve- ment at around 240 mV. This 2M 65 nm SRAM chip can operate at 0.7 V with the help of the on-chip VDC. Furthermore, with the programmability of the VDC, we can optimize the read margin and write margin separately to have dramatic yield improvement. In the advancement of CMOS technology, the VDC approach can improve the future SRAM cell operation without additional external power supplies and complicate design modification.