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3-D Capacitive Interconnections for Wafer-Level and Die-Level Assembly
提出基于电容耦合的3D互连方案，实现高带宽低能耗通信。
1.23 Gb/s带宽, 19 Mb/s/μm²吞吐密度, 0.14 mW/Gb/s能耗
3D互连电容耦合同步通信晶圆级组装芯片级组装
▸创新点1：基于预充电和传输的同步通信电路设计，该方法通过预充电阶段减少信号传输延迟，显著提高了数据传输速率，实验结果显示最高通信带宽达到1.23 Gb/s。
▸创新点2：优化互连灵敏度的电路设计，通过电容耦合技术降低了信号传输中的噪声干扰，实现了高可靠性通信，误码率测试表明在超过10^49比特传输中无错误。
▸创新点3：支持晶圆级和芯片级组装的3D互连方案，该方案在0.13微米CMOS工艺下实现，面积占用仅为8x8微米，展示了其在紧凑空间中的高效集成能力。
▸创新点4：低能耗设计，通过优化的电路结构和信号处理技术，实现了0.14 mW/Gb/s的能耗效率，为高密度集成提供了节能解决方案。
Abstract
This paper presents a 3-D interconnection scheme based on capacitive coupling. We propose synchronous com- munication circuits, based on a precharge and transmission approach, that provide an optimization of interconnection sen- sitivity. Measurements on a 0.13 m CMOS implementation demonstrate working connections with an area occupation of 8 8 m/50. Experimental results are presented for both die-to-die and wafer-to-wafer assembly techniques. They show a max- imum communication bandwidth of 1.23 Gb/s, leading to a throughput per area of 19 Mb/s/ m/50with an energy consumption of 0.14 mW/Gb/s. BER measurements demonstrate the reliability of these AC interconnections with no error on more than 10 /49/51bits transmitted.