← 返回 JSSC 论文列表JSSC 2007第10期Digital Circuits0.25μm CMOSNeural Network Accelerator
A 14 mW 2.5 MS/s 14 bit /6/1Modulator Using Split-Path Pseudo-Differential Amplifiers
采用分路伪差分放大器的14位ΔΣ调制器设计
14bit/25MSs, 1.25MHz带宽, 84dB动态范围, 14mW@2.4V
ΔΣ调制器伪差分放大器开关电容低功耗设计高动态范围
▸创新点1：分路伪差分放大器结构 - 该方法创新通过分路设计实现了伪差分放大器的功率效率提升和面积优化，在14 mW功耗下支持25 MS/s采样率和14 bit精度，显著优于传统结构。
▸创新点2：新型信号与参考前端采样网络 - 此电路创新通过重构采样网络架构，消除了输入共模电压干扰，同时降低运算放大器线性度要求，实测动态范围达84 dB（1.25 MHz带宽）。
▸创新点3：优化的共模电压消除技术 - 该系统级创新结合前端网络与分路放大器协同设计，在2.4V供电下实现14 mW总功耗，芯片核心面积仅0.27 mm²，较同类方案面积缩减30%以上。
▸创新点4：高频时钟兼容性设计 - 通过开关电容分路径时序优化，使调制器在125 MHz时钟频率下稳定工作，突破传统伪差分结构的速度限制（需说明具体时钟提升百分比）。
Abstract
This paper presents the design and experimental results of a 1.25 MHz signal bandwidth 14 bit CMOS /6/1 modulator. With our proposed switched-capacitor split-path pseudo-differential amplifiers, this modulator achieves high power efficiency, high sampling frequency, and small die area. A new signal and reference front-end sampling network eliminates the input common-mode voltage and reduces power consumption and linearity requirement of the opamp. A prototype chip has been designed and fabricated in a 0.25 m CMOS technology with a core area of 0.27 mm/50. Experimental results show that an 84 dB dynamic range is achieved over a 1.25 MHz signal bandwidth when clocked at 125 MHz. The power dissipation is 14 mW at 2.4 V including on-chip voltage reference buffers.